Modeling wire delay, area, power, and performance in a simulation infrastructure

We present Justice, a set of extensions to the Liberty simulation infrastructure that model area, wire length, and power consumption in processor architectures. Given an architectural specification of a processor, Justice estimates the area of each module of the processor and generates a floorplan of the processor. From the floorplan, Justice computes the length and delay of critical communication paths in the architecture. It then modifies the architectural specification by adding delay elements on communication paths whose delay is one or more clock cycles. This modified architectural description is passed back to the Liberty infrastructure, which creates a simulator for the architecture. Justice also estimates the per-access power consumption of each module in an architecture and inserts activity counters to measure how often modules are used. After simulation, a post-processing pass computes the total power consumed by each module and overall power consumption. To illustrate the capabilities of Justice, we simulate a number of VLIW processors and analyze the tradeoffs between power, performance, and wire length in these architectures. In particular, we show that the architectures that have the highest performance when wire length is neglected become some of the worst performers when wire delay is considered and clock rate increased.